1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming metal silicide regions on semiconductor devices that involve performing at least one millisecond anneal process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
In a field effect transistor, metal silicide regions are typically formed in the source/drain regions of a transistor to reduce the resistance when a conductive contact is formed to establish electrical connection to the source/drain regions. FIGS. 1A-1D depict one illustrative prior art method for metal silicide regions on a transistor device 10. As shown in FIG. 1A, the basic transistor structure 10 is formed in and above a semiconducting substrate 12 in an active area defined by a shallow trench isolation structure 14. At the point of fabrication depicted in FIG. 1A, the device 10 includes a gate insulation layer 16, a polysilicon gate electrode 18, sidewall spacers 19 and source/drain regions 20 formed in the substrate 12. The source/drain regions 20 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate 12 using known masking and ion implantation techniques.
Next, as shown in FIG. 1B, a layer of metal 22, such as nickel, cobalt, titanium, platinum, etc., or a combination of such materials, is deposited above the device such that it contacts the exposed portions of the silicon-containing source/drain regions 20 and the polysilicon gate electrode 18. In some cases, a pre-amorphization ion implant process may be performed on at least the source/drain regions 20 prior to the formation of the layer of metal 22. The pre-amorphization implant process is typically performed with relatively large inert ions, and the purpose of such an implant process is to make the implanted region more receptive to the formation of a metal silicide region therein.
FIG. 1C depicts the device 10 after a first rapid thermal anneal (RTA) process was performed at a temperature that falls within the range of about 220-300° C. (for NiSi) for a duration of about 1.5 seconds or longer. During this first RTA process, the metal in the layer of metal 22 reacts with the silicon in the silicon-containing regions contacted by the layer of metal to thereby form a relatively higher resistance form of metal silicide 24, e.g., a nickel disilicide (NiSi2), in the portions of the source/drain regions 20 and the gate electrode 18 that are in contact with the layer of metal 22.
FIG. 1D depicts the device 10 after several process operations were performed. First, portions of the layer of metal 22 that did not react with the underlying silicon-containing materials during the first RTA process are removed by performing a standard stripping process. After the removal of the unreacted portions of the layer of metal 22, a second rapid thermal anneal (RTA) process is performed on the device 10 at a temperature that falls within the range of about 400-500° C. (for NiSi) for a duration of about 1.5 seconds or longer. This second RTA process converts the relatively higher resistance silicide region 24 into a relatively lower resistance silicide region 24A, e.g., nickel monosilicide (NiSi), that is positioned in the source/drain regions 20 and in the gate electrode 18. While this basic silicide formation process is depicted as being formed on the entire exposed surface area of the source/drain regions 20, in more advanced and more densely packed integrated circuit products, the silicide layer 24A may only be formed on the portion of the source/drain regions 20 that is exposed when a contact opening is formed in a layer of insulating material so as to establish electrical contact to the source/drain region by the ultimate formation of a conductive contact in the contact opening.
In an effort to reduce the temperatures necessary to form metal silicide regions, manufacturers utilize a concept known as “ion beam mixing” (IBM), which will be simplistically described with reference to FIGS. 1E-1F. FIG. 1E depicts an enlarged view of a portion of the substrate 12 where the above-described layer of metal 22 will be formed so as to ultimately form a metal silicide region 24A in the substrate 12. In general, prior to the formation of the layer of metal 22, the surface of the substrate 12 is cleaned as thoroughly as possible in an attempt to insure that the surface is free of all foreign materials. Despite the best efforts of manufacturers, a very thin layer of silicon dioxide 30, sometimes referred to as an interfacial oxide layer, will normally form on the substrate 12 after it has been cleaned and before the layer of metal 22 can be formed on the substrate 12. Although the layer of silicon dioxide 30 is depicted as being uniformly formed across the surface of the substrate 12, it may not be so uniformly formed in all application. The presence of the layer of silicon dioxide can undesirably increase the resistance of the final silicide region 24A.
Ion beam mixing generally involves irradiating the interface between the layer of metal 22 and the substrate 12 with a beam of silicon or other ions prior to performing an annealing step. FIG. 1F schematically depicts an illustrative ion beam mixing process 32 wherein silicon atoms 32A are introduced at or near the interface between the metal layer 22 and the substrate 12. Accordingly, the interface, and the demarcation between two materials at the interface juncture, can be “smeared” by the silicon ions. Reaction between the two materials on either side of the smeared junction can thereby proceed at a lower temperature.
The present disclosure is directed to various methods of forming metal silicide regions on semiconductor devices that involve performing at least one millisecond anneal process that may solve or at least reduce one or more of the problems identified above.